1. Field of the Invention
The present invention relates to a semiconductor memory including nonvolatile memories having charge-trapping gate insulating films and a method for manufacturing the same.
2. Description of Related Art
One of known electrically writable nonvolatile memories is a memory in which an interconnection layer made of a diffusion layer also functions as a source/drain of a memory transistor (virtual ground structure).
In recent years, semiconductor devices have been designed under hyperfine rules to provide highly-integrated structure, high performance and high reliability. In particular, it is very important to achieve high reliability in fine nonvolatile memories.
FIG. 26 illustrates a typical structure of memory cells 200 having charge-trapping gate insulating films. Bit lines 202 made of a diffusion layer are formed on a semiconductor substrate 201 and bit line oxide films 210, charge-trapping gate insulating films 203 and word lines 204 are formed thereon to provide memory cells 200.
The memory cells 200 are operated in the following manner. For data writing in the memory cell 200, electrons are injected into the gate insulating film 203. The injected electrons are trapped in the gate insulating film 203, thereby increasing threshold voltage Vt. The electrons injected are hot electrons generated near the bit lines 202. Data erasing is performed by injecting holes in the gate insulating film 203. The injected holes neutralize the electrons trapped in the gate insulating film 203, thereby decreasing Vt. The holes are injected using BTBT (Band To Band Tunneling) current generated near the bit lines 202.
After the memory cells 200 have been fabricated, wires for driving the memory cells 200 are formed. The wire formation is carried out by plasma etching, which generates UV light. The UV light may generate excited electrons when it enters the semiconductor substrate provided with the memory cells.
In recent years, the entry of the excited electrons into the gate insulating film 203 has been pointed as a problem because it decreases the reliability of the memory cells 200. As described above, the data writing into the memory cells 200 is performed by injecting the electrons into the gate insulating film 203. If the excited electrons generated by the UV light enter the gate insulating film 203, it means that an excess of the electrons are injected. Therefore, the Vt exceeds a predetermined value. Further, even if a predetermined amount of holes are injected into the gate insulating film 203 for data erasing, the electrons trapped in the gate insulating film 203 cannot be neutralized completely. Therefore, the Vt is not reduced to a predetermined value.
In particular, the neutralization of the electrons trapped in the gate insulating film 203 is performed by injecting the holes into the gate insulating film 203 using the BTBT current generated near the bit lines 202. Therefore, if unwanted excited electrons are trapped around the middle of the gate insulating film 203, they are hardly neutralized. In the case of a floating gate, however, the unwanted electrons, if injected in the floating gate, are easily erased by applying the UV light.
For the above-described reasons, the entry of the excited electrons generated by the UV light into the gate insulating film 203 makes it significantly difficult to adjust Vt by writing and erasing data in and from the memory cells 200. This leads to a decrease in reliability of the memory cells 200.
As a solution to this problem, there is a known method for forming a light blocking film in advance above the memory cells 200 to prevent the entry of the UV light generated during the formation of the wires.
FIGS. 27A and 27B are sectional views illustrating the structure of a semiconductor memory in which a light blocking film is formed over the memory cells. FIG. 27A shows the neighborhood of bit line contact plugs 209 and FIG. 27B shows the neighborhood of word line contact plugs 212.
As shown in FIGS. 27A and 27B, an interlayer insulating film 206 is formed over the memory cells 200 and a light blocking film 205 is formed on part of the interlayer insulating film 206 covering the memory cells 200. The light blocking film 205 prevents the UV light generated during the formation of wires (not shown) on the interlayer insulating film 206 from entering the neighborhood of the memory cells 200, thereby preventing the injection of unwanted excited electrons into the gate insulating film 203 in the memory cells 200.
The semiconductor memory shown in FIGS. 27A and 27B is fabricated by a method shown in FIGS. 28A to 28D.
First, as shown in FIG. 28A, bit lines 202 made of a diffusion layer are formed on a semiconductor substrate 201 and bit line oxide films 210, charge-trapping gate insulating films (not shown) and word lines 204 are formed thereon by a general technique to provide memory cells 200.
Then, as shown in FIG. 28B, an interlayer insulating film 206 and a light blocking film 205 are deposited over the memory cells 200. Then, the light blocking film 205 is partially removed using a photomask 213 such that the light blocking film 205 remains only above the memory cells 200 as shown in FIG. 28C.
Then, as shown in FIG. 28D, an insulating film 207 is deposited over the light blocking film 205 and contact holes are formed through the insulating film 207 and the interlayer insulating film 206 to reach the bit lines 202. Wiring material is then buried in the contact holes to form bit line contact plugs 209.
The light blocking film 205 is a conductive film such as an amorphous silicon film or a tungsten film. Therefore, the light blocking film 205 has to be separated from the bit line contact plugs 209 to prevent a short circuit between the bit line contact plugs 209.
As a result, during the formation of the wires on the insulating film 207 after the bit line contact plugs 209 have been provided, UV light passes through part of the insulating film 207 between the light blocking film 205 and the bit line contact plugs 209 to reach the neighborhood of the memory cells. This leads to an increase in Vt of the memory cells near the bit line contact plugs 209.
Further, if the distance between the bit line contact plugs 209 and the memory cells is increased to avoid the rise in Vt due to the entry of the UV light, the total area occupied the semiconductor memory increases.
As a solution to this, U.S. Pat. No. 6,833,581 describes a method for blocking the above-described entry path of the UV light. Detailed description thereof is provided below with reference to FIG. 29.
Referring to FIG. 29, an interlayer insulating film 206 and a light blocking film 205 are formed over the memory cells 200 and bit line contact plugs 209 are formed to penetrate the light blocking film 205 and the interlayer insulating film 206. The light blocking film 205 is made of an insulating film such as a silicon-rich oxide film or a silicon-rich nitride film. Therefore, even if the light blocking film 205 contacts the bit line contact plugs 209, a short circuit does not occur between the bit line contact plugs 209.
With the thus formed light blocking film 205, the entry path of the UV light generated during the formation of the wires on the interlayer insulating film 206 is blocked by the light blocking film 205 and the bit line contact plugs 209. This prevents the injection of unwanted excited electrons into the gate insulating film 203 in the memory cells 200.
The semiconductor memory shown in FIG. 29 is fabricated by the method shown in FIGS. 30A to 30D.
First, as shown in FIG. 30A, bit lines 202 made of a diffusion layer are formed on a semiconductor substrate 201 and bit line oxide films 210, charge-trapping gate insulating films 203 and word lines 204 are formed thereon by a general technique to provide memory cells 200.
Then, as shown in FIG. 30B, an interlayer insulating film 206 and a light blocking film 205 are deposited over the memory cells 200. Then, contact holes 215 reaching the bit lines 202 through the light blocking film 205 and the interlayer insulating film 206 are formed using a photomask 214 as shown in FIG. 30C.
Then, as shown in FIG. 30D, wiring material is buried in the contact holes 215 to form bit line contact plugs 209. Thus, the semiconductor memory shown in FIG. 29 is obtained.